A PLD is a semiconductor integrated circuit that contains logic circuitry that can be programmed (“designed”) by a user to perform a host of logic functions. An FPGA is an example of a PLD that may benefit from the presently disclosed system design tools and techniques. An application specific integrated circuit (ASIC) that include one or more programmable sections is a further example of a PLD. The assignee of the present invention develops and manufactures PLDs including those that incorporate embedded processors, and complex programmable logic devices (CPLDs). These semiconductor integrated circuits, or chips, may be designed by a purchaser (“user”) for use in the user's own electronic systems.
Normally, reconfiguring a designed PLD requires the PLD user to place the PLD in a reset mode while a controller is used to load a different design onto it. “Partial reconfiguration” of a PLD, as the term is used herein and in the claims, means making a change to a portion of a PLD while at least one other portion is still operating. Partial reconfiguration allows for some parts of the designed PLD to continue operating while a controller loads a partial design into another portion of the PLD. The controller may be within an operating portion of the PLD or within an external component. Thus, a “partially reconfigurable” PLD is a type of PLD that supports partial reconfiguration such that a portion of the partially reconfigurable PLD may be reconfigured while at least one other portion of the partially reconfigurable PLD is still operating.
Partial reconfiguration provides various benefits to the user, including reduction in the size, cost, and power consumption of the PLD and improved fault tolerance/reliability. For example, using a partial reconfiguration technique permits selectively powering down parts of a PLD, while the remainder of the PLD continues to operate normally.
PLDs have been developed that include logic for performing data encoding and decoding in the context of, for example, videoconferencing. A large number of codec standards have evolved and continue to be developed for encoding, decoding, compressing and decompressing video data streams. For example, MPEG2, MPEG4, H.263, H.264, VP6, VP8, Real, VC1/WMV9 are well known codec standards that may be employed by one or more videoconference participants. At least some participants of any particular videoconference may be participating from disparate physical and/or logical locations (“stations”) that are communicatively coupled, directly or indirectly. In some implementations, the stations may be communicatively coupled by way of a network, for example, a local area network, a wide area network, the Internet, or the public switched telephone network, for example. A multipoint control unit (MCU) may provide interoperability between multiple participants notwithstanding that not all participants are necessarily using the same codec, or even a codec that is pre-identified to the MCU. As a result, the MCU may need to be capable of recognizing and appropriately responding, in real time, to a large number of codec standards.
In the absence of the present teachings, a requirement that the MCU be able to accommodate any of such a large number of codec standards may impose a significant burden on the processing capabilities of the MCU and adversely affect the cost and performance of the MCU. As a result, there is a need for techniques that reduce that burden.